Embodiments relate to a method for manufacturing a semiconductor device.
As semiconductor devices become more highly integrated, a size of the internal transistors has been gradually reduced. However, there may a limitation regarding how much a junction depth of a source/drain of a transistor can be reduced.
This is because a channel length reduces from a long channel to a short channel of a length less than 0.5 μm, a depletion region of the source/drain may penetrate into the channel to shorten an effective channel length, reduce a threshold voltage, and may thus cause a short channel effect, which may ultimately lead to a loss of a gate control over the metal oxide semiconductor (MOS) transistor.
There may be ways to reduce or prevent the short channel effect. For example, reducing a thickness of a gate insulating layer and a maximum width of a channel between a source and a drain, i.e., a maximum width of a depletion region under a gate, and reducing impurity concentration within the semiconductor substrate may help to reduce or prevent the short channel effect.
It may also be important to form a shallow junction. For this purpose, an ion implantation apparatus and a subsequent heat treatment process for forming a shallow junction in a manufacturing process of a semiconductor device are being developed.
A related art method for manufacturing a semiconductor device will be described below with reference to the accompanying drawings.
FIGS. 1A to 1E are cross-sectional illustrations of a related art method for manufacturing a semiconductor device.
Referring to FIG. 1A, semiconductor substrate 21 may include an active region and a device isolation region. Device isolation layer 22 may be formed in the device isolation region through a local oxidation of silicon (LOCOS) or a shallow trench isolation (STI) process.
Semiconductor substrate 21 may be thermally oxidized at a high temperature to form the gate oxide layer 23, and a polysilicon layer may be deposited on the gate oxide layer 23.
Also, the polysilicon layer and the gate oxide layer may be selectively etched, for example by a photolithography process to form gate electrode 24.
Referring to FIG. 1B, oxide layer 25 may be formed on a surface of semiconductor substrate 21 including gate electrode 24.
Low concentration impurity ions may be implanted into an entire surface of semiconductor substrate 21 using gate electrode 24 as a mask, and may form lightly doped drain (LDD) region 26 in portions of semiconductor substrate 21 located at both sides of gate electrode 24.
LDD region 26 may expand into a portion of the semiconductor substrate located under the gate electrode through diffusion of the impurity ions, and may overlap gate electrode 24.
Referring to FIG. 1C, oxide layer 25 may be removed, and first insulating layer 27 and second insulating layer 28, which may have different etch selectivities may be sequentially formed on a surface of semiconductor substrate 21 including gate electrode 24.
First insulating layer 27 may be formed of oxide and second insulating layer 28 may be formed of nitride.
Removal of oxide layer 25 may influence a quality of gate oxide layer 23, may increase the divot depth of the device, and thus may influence the device performance.
Referring to FIG. 1D, an etch back process may be performed on entire surfaces of first and second insulating layers 27 and 28 to form first and a second insulating layer sidewalls 27a and 28a. 
Referring to FIG. 1E, high concentration impurity ions may be implanted into an entire surface of semiconductor substrate 21 using gate electrode 24, first insulating layer sidewall 27a, and second insulating layer sidewall 28a as a mask and may form source/drain impurity regions 29 connected to LDD region 26 in semiconductor substrate 21.
Thereafter, though not shown, an interlayer insulating layer, a metal line and the like may be formed to complete a logic process.
However, a related art method for manufacturing a semiconductor device may have certain problems.
For example, the overlapping of the LDD region and a bottom of the gate electrode may cause gate induced drain leakage (GIDL) and parasitic capacitance, which may deteriorate the performance of a device.
Also for example, because only the oxide layer formed on the entire surface of the semiconductor substrate serves as a barrier when the LDD region is formed, the barrier oxide layer may not assist a process related to forming a shallow junction aside from providing surface protection.